Abstract

 In this paper, hardware implementation of the IEEE 802.22 Interleaver is presented. The key challenge in implementing the interleaver is its address generator unit as other units implementation is straightforward. The fully-combinational and combinational-sequential architectures of the address generator are designed using VHDL and compared in terms of area, timing, and power. Simulation results show that the second approach result in 70% improvement in area compared to the first approach even though operates two times slower. In addition power consumption of the combinational-sequential method is more acceptable for wireless applications. Moreover, both methods meet the standard requirements.