Abstract

The parallel structure of matrix multipliers makes them fascinating candidates to benefit from memristors’ high density architecture. This paper first explains a memristor-based analog vector–matrix multiplier suitable for approximate computing. According to the existence of fast and efficient converters, namely, DACs and ADCs, in the field of approximate computing and the programmability of memristors, the presented vector–matrix multiplier is combined with digital circuits which it leads to a matrix–matrix multiplier as an extension. In this work, opamps’ characteristics such as power and speed, distribution of matrix elements, and memristors’ faults have been considered and their effects on performance, accuracy, and efficiency of the proposed multiplier have been analyzed. Also, a new structure for handling negative numbers has been proposed. All the circuits have been simulated using ‘‘Ngspice mixed-signal circuit simulator’’ in C?? programming environment. The simulation results revealed that the multiplier’s analog core brought gains in terms of performance and energy when acceptable ranges of inaccuracies in results could be tolerated.